verilog - Assigning values of 4*4 matrix -

i'm trying create 4*4 matrix in form:

2 3 1 1
1 2 3 1
1 1 2 3
3 1 1 2

then need assign values element in each location multiply 4 inputs each 1 8 bits.

a0, a1, a2, a3 

i have tried write code :

module mix_nibbles_matriex(   out_0,out_1,out_2,out_3,nibble_0,nibble_1,nibble_2,nibble_3,   clk,rst,load   );    input clk,rst,load ;   output reg [7:0] out_0,out_1,out_2,out_3;   input [7:0] nibble_0,nibble_1,nibble_2,nibble_3;    //wire matrix[3:0][0:3];    reg [1:0][7:0] a_unpacked_array[4];    @( posedge clk or negedge rst)   if (!rst)     a_unpacked_array[0][0]=0;   else if (load)     assign a_unpacked_array[0][0]=2;     assign a_unpacked_array[0][1]=3;     assign a_unpacked_array[0][2]=1;     assign a_unpacked_array[0][3]=1;      assign a_unpacked_array[1][0]=2;     assign a_unpacked_array[1][1]=3;     assign a_unpacked_array[1][2]=1;     assign a_unpacked_array[1][3]=1;      assign a_unpacked_array[2][0]=2;     assign a_unpacked_array[2][1]=3;     assign a_unpacked_array[2][2]=1;     assign a_unpacked_array[2][3]=1;      assign a_unpacked_array[3][0]=2;     assign a_unpacked_array[3][1]=3;     assign a_unpacked_array[3][2]=1;     assign a_unpacked_array[3][3]=1;      //display ("a_unpacked_array      = %b", a_unpacked_array); endmodule 

i'm still have these errors:

error:hdlcompiler:939 - "d:/embedded_project/mix_nibbles_matriex.v" line 38: single value range not allowed in mode of verilog
error:hdlcompiler:1439 - "d:/embedded_project/mix_nibbles_matriex.v" line 38: multiple packed dimensions not allowed in mode of verilog
error:hdlcompiler:1417 - "d:/embedded_project/mix_nibbles_matriex.v" line 44: bit-select or part-select not allowed in assign statement non-net a_unpacked_array
error:hdlcompiler:598 - "d:/embedded_project/mix_nibbles_matriex.v" line 27: module ignored due previous errors.

there couple problems code.

1. verilog doesn't support multiple packed dimensions. you'd need use systemverilog make construct work. can follow @greg suggestion use unpacked dimension.
2. reg [1:0][7:0] a_unpacked_array[4]; - compiler tries treat 4 range, single value range not allowed. maybe meant [3:0]? [1:0] should [3:0].

3. your always block has issues: missing begin-end, unnecessary assign keywords, etc.:

   always @(posedge clk or negedge rst)   if (!rst) begin     a_unpacked_array[0][0] <= 0;     //...   end else if (load) begin     a_unpacked_array[0][0] <= 2;     //...   end