arrays - Order of size specifiers in unpacked ports -

i wondering difference in declaring unpacked port way:

input logic a[10]; 

or way:

input logic a[9:0]; 

i not find difference documented anywhere, know experience connecting 2 ports these "different?" types not cause warning (tested in both vcs , modelsim) order of data might reversed.

in verilog input logic a[10] logic not allowed , cause

single value range not allowed in mode of verilog

error. need declare array using range (i.e. [9:0]).

on other hand, in systemverilog can declare array using range or size (i.e. [10]). based on ieee 1800-2012 ch. 7.4.2:

each fixed-size dimension shall represented address range (...) or single positive number specify size of fixed-size unpacked array, in c. in other words, [size] becomes same [0:size-1].