verilog - Multiplying two 32 bit numbers using 32 bit carry look ahead adder -

i have tried write code in verilog multiply 2 32 bit binary numbers using 32 bit carry ahead adder program fails compile. the generate if condition must constant expression error keeps on coming in modelsim part 'if(store[0]==1)' , 'if(c[32]==1)'

this algorithm followed:

begin program multiplier = 32 bits multiplicand = 32 bits register = 64 bits put multiplier in least significant half , clear significant half = 1 32 begin loop if least significant bit of 64-bit register contains binary ‘1’ begin if add multiplicand significant half using claa begin adder c[0 ] = ’0’ j = 0 31 begin loop calculate propagate p[j] = multiplicand[j]^ significant half[j] calculate generate g[j] = multiplicand[j]·most significant half[j] calculate carries c[i + 1] = g[i] + p[i] · c[i] calculate sum s[i] = p[i] Å c[i] end loop end adder shift 64-bit register 1 bit right  throwing away least significant bit else shift 64-bit register 1 bit right throwing away least significant bit end if end loop register = sum of partial products end program 

code:

module multiplier_32(multiplier,multiplicand,store);   output store;   input [31:0]multiplier,multiplicand;   wire [63:0]store;   genvar i,j;   wire g=32;   wire [31:0]p,g,sum;   wire [32:0]c;   assign store[31:0]=multiplier;    generate for(i=0;i<32;i=i+1)   begin     if(store[0]==1)     begin       assign c[0]=0;       for(j=0;j<32;j=j+1)       begin         assign p[j]= multiplicand[j]^store[g];         assign  g[j]=multiplicand[j]&store[g];         assign  c[j+1]=g[i]|(p[i]&c[j]);         assign  sum[j]=p[i]^c[j];         assign g=g-1;       end        assign store[63:32]=sum[31:0];        if(c[32]==1)       begin         assign store[62:0]=store[63:1];         assign store[63]=1;       end       else        begin         assign store[62:0]=store[63:1];         assign store[63]=0;       end     end     else     begin       assign store[62:0]=store[63:1];       assign store[63]=0;         end   end endgenerate  endmodule 

a generate block evaluated @ compile/elaboration time. used construct hardware patterns , not evaluate logic. value of store[0], c[32], , other signals unknown @ time. know values parameters , genvars.

in case, combinational block (always @*) fulfill functionality requirements. replace wire reg, assignments inside always @*, , remove assign keywords (assign should not used inside always block).

module multiplier_32(     input [31:0] multiplier, multiplicand,     output reg [63:0] store   );  integer i,j; integer g; reg [31:0] p,g,sum; reg [32:0] c;  @* begin   g = 32;   store[31:0]=multiplier;   for(i=0;i<32;i=i+1) begin     // code here, not use 'assign'   end end endmodule