loops - Why is this variable not considered a constant? -

the following code wrote test bench simulate decoder (verilog hdl). converts [15:0]ir [25:0]controlword. literal byproduct watched well.

all values 0-65535 need tested 16-bit ir variable. in beginning of loop, distinctly assign ir 0, quartus telling me that:

warning (10855): verilog hdl warning @ controluni_tb.v(20): initial value variable ir should constant

and result following:

error (10119): verilog hdl loop statement error @ controluni_tb.v(23): loop non-constant loop condition must terminate within 250 iterations

the code test bench module follows:

module controluni_tb;   reg [15:0]ir;   reg clock;   wire [25:0]controlword;   wire [15:0] literal;   total_control_unit_2 dut (ir,controlword,literal);    initial   begin     clock <= 1'b0;   end    initial   begin     ir <= 16'b0;   end    initial   begin     forever     begin       #1 ir <= ir + 16'b1;     end   end    initial     #65535 $finish; endmodule  

your code has no errors. initial blocks , system functions ($finish) used simulation (not synthesis). error related synthesis. edited code more readability (your clock zero!) :

module controluni_tb;     reg [15:0]ir;     reg clock;     wire [25:0]controlword;     wire [15:0] literal;      total_control_unit_2 dut (ir,controlword,literal);      initial begin         clock = 1'b0;     end      initial begin         ir = 16'b0;         forever #1 ir = ir + 16'b1;     end      initial begin         #65535 $finish;     end endmodule