Makefile always compile no mater new or old -

the following makefile:

cc      = gcc clang   = clang   flags   = -wall -ggdb   cflags  = -g -fsanitize=address     target  = doublefree usefree      .phony: clean   : $(target)   % : %.c       $(cc) $(flags) -o $(addsuffix -gcc,$@) $<       $(clang) $(cflags) -o $(addsuffix -clang,$@) $<   clean :        $(foreach var,$(target),rm -f $(addsuffix -gcc,$(var)) $(addsuffix -clang,$(var))) target : prerequisites model 

when make all, compile file in $(target) list, no matter file new or old! why happen?

you have rule:

%: %.c     ... 

so when make must build foo, believes rule suffice. @ commands:

% : %.c       $(cc) $(flags) -o $(addsuffix -gcc,$@) $<       $(clang) $(cflags) -o $(addsuffix -clang,$@) $< 

this rule not build foo; builds foo-gcc , foo-clang. next time run make, make sees needed foo not exist , attempts build it-- using rule again.

edit:

i recommend this:

targets  = doublefree usefree  : $(addsuffix -gcc, $(targets)) $(addsuffix -clang,$(targets))  %-gcc : %.c     $(cc) $(flags) -o $@ $<    %-clang : %.c     $(clang) $(cflags) -o $@ $<