vhdl - How can I write sequential component with case -

below code not compiling. how can modify make works? thank you.

case s when '0' => u1: hi port map (x,y,z); when others => u2: hey port map (x,y,z); end case; 

without rest of code there guessing, have used case outside process, "illegal concurrent statement" message, since case statement can used in process. however, component instantiation port map (x,y,z) concurrent statement, can used outside process.

vhdl not programming language, hardware description language (the hdl part of vhdl), when writing vhdl code, think of describing electrical circuit, , in parts fixed, signal values can vary on time.

so, instantiate components outside process port map (x,y,z) , control signal values processes, other components, ports, etc.